by Piotr Koziuk | Feb 4, 2026 | Blog+blog, Blog+UCIe
Introduction When discussing Universal Chiplet Interconnect Express (UCIe) a lot of, well deserved, focus is placed on the UCIe PHY itself with power and throughput performance, and physical aspects like bump pitch and area utilization. On top of this the second focus... 
by Piotr Koziuk | Jan 8, 2026 | Blog+blog, Blog+JESD
Overview The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with... 
by Piotr Koziuk | Dec 10, 2025 | Blog+blog
Introduction Ultra Accelerator Link (UA Link) standard has been specified to enable the creation of systems comprised of multiple nodes targeting AI applications. The UA Link Protocol and interfaces are defined to support low latency Accelerator to Accelerator... 
by Piotr Koziuk | Nov 3, 2025 | Blog+blog
Introduction This article will introduce the main concepts of the Digital Intermediate Frequency Interoperability (DIFI) standard including the new features introduced in version 1.3. With no assumptions of prior knowledge from the reader this should serve as an... 
by Piotr Koziuk | Oct 6, 2025 | Blog+blog, Blog+JESD
Where in the JESD world is bitstream alignment? Bitstream alignment is a function of the Receiver (RX), as seen in the figure below it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic...