Blog
UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
When discussing Universal Chiplet Interconnect Express (UCIe) a lot of, well deserved, focus is placed on the UCIe PHY itself with power and throughput performance, and physical aspects like bump pitch and area utilization…
JESD204 Frame Mapping explained from converter samples to lanes
The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with…
UA Link PCS customizations from 800GBASE-R Ethernet PCS Clause 172
Introduction Ultra Accelerator Link (UA Link) standard has been specified to enable the creation of systems comprised of multiple nodes targeting AI applications. The UA Link Protocol and interfaces are defined to support low latency Accelerator to Accelerator...
Why What Where DIFI and the new version 1.3
Introduction This article will introduce the main concepts of the Digital Intermediate Frequency Interoperability (DIFI) standard including the new features introduced in version 1.3. With no assumptions of prior knowledge from the reader this should serve as an...
Multiple ways JESD204 performs bitstream alignment
Bitstream alignment is a function of the Receiver (RX), it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes
UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
AI and high-performance computing (HPC) workloads are growing steadily and the need for establishing high performance and low-latency interconnect links is placing pressure on interconnect technology.