CPRI 7.0
Highly mature, silicon proven and silicon agnostic IP core conforming to CPRI 7.0 specifications
Overview
Chip Interfaces Common Public Radio Interface (CPRI) 7.0 core is a silicon agnostic implementation of the CPRI 7.0 specification, which is targeting both ASIC and FPGAs CPRI. CPRI is a high-speed serial interface designed to meet or exceed the requirements of base band systems, C-RAN switches, Digital Front-End (DFE) processors or advanced test systems. With its extreme flexibility and reduced logic consumption, the CPRI 7.0 IP core is the perfect match whether the application is REC (Radio Equipment Controller) or RE (Radio Equipment).
The core can be dynamically configured to handle wireless multi-mode radio systems implementing deterministic latency features and high-performance throughputs required by LTE-A and 5G radio base stations.
The CPRI cores come in several versions to suit any implementation scenario whether speed, a compact size or a wide feature set is required.
Key Features
Delivering Performance
- CPRI Specification V7.0 full feature set implemented
- Modular design with full feature set available
- Up to 64 antenna carriers per core
- Supports line-rates 1-10 (up to 24.33024 Gbps)
- Dynamic mapping configuration
Richly Featured
- All mapping methods available (1, 2 and 3)
- Size optimized Ethernet GMII interface
- Accurate delay measurements and calibration
- Daisy Chaining Interface
- Rate Auto-Negotiation
- RS-FEC
- Scrambling
- PCS with Delay Measurement 64B 66B
- Sample Widths 8-16 bits
Easy to use
- Testbench with typical system configuration and examples
- Easy integration
Silicon Agnostic
- Designed in VHDL and targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Synopsys Lint and CDC (optional)
Block Diagram
CPRI 7.0 IP is developed to be silicon agnostic and can easily be tested in FPGA before integration into ASIC. The Architecture is optimized to support higher speed of CPRI 7.0, and has been hardware validated to deliver a robust solution.
CPRI 7.0 Advantages & Benefits
Test Environment
CPRI 7.0 IP is tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Optimized for ASIC but can be synthesized for most FPGAs
Interoperability Tested
Multiple field deployments and tested against CPRI references
Radio Expertise
IP with rich feature set designed by pioneers in radio solutions
Active Support
All support is actively provided by engineers directly
Solutions at Work
CPRI used in both 4G and 5G radio solutions
For 4G remote radio heads CPRI is an essential component for connectivity to the baseband.
CPRI used in aggregators for mapping and demapping of CPRI legacy connectivity into Ethernet
Advent of 5G coupled with new functional splits between the based and radio, has made the building of a packet based fronthaul system a possibility.
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
CPRI used in both 4G and 5G radio solutions
For 4G remote radio heads CPRI is an essential component for connectivity to the baseband. The CPRI is providing full synchronization and supports line rates up to 24Gbps. Chip Interfaces has deployed multiple solutions for RRH digital front ends (DFE's) and has a deep understanding of the radio design and the associated standards.
CPRI used in aggregators for mapping and demapping of CPRI legacy connectivity into Ethernet
Advent of 5G coupled with new functional splits between the based and radio, has made the building of a packet based fronthaul system a possibility. This packet based fronthaul system can be achieved either by converting the CPRI streams into eCPRI using baseband processing or mapping of CPRI frames into Ethernet Packets also known as Radio over Ethernet (RoE).
Chip Interfaces have proven solutions available for RoE that can convert CPRI into formats that can be transported on Ethernet and be used to aggregate traffic from different sources like eCPRI and CPRI into the same transport link.