eCPRI

Size optimized, silicon agnostic IP core suitable for line rates upto 25G

Overview

eCPRI core from Chip Interfaces is a highly scalable and silicon agnostic implementation of the eCPRI standard targeting any ASIC or FPGA technologies. The eCPRI implementation builds on Chip Interfaces long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.

The IP is designed to meet or exceed the requirements of radio systems, base band systems, fronthaul switches or advanced test systems. The speed optimized core can handle any solutions reaching from the “small footprint” to the most complex applications running 25 Gbps. The IP can dynamically be configured to handle wireless multi- mode radio systems enabling high-performance throughputs required by 4G and 5G wireless solutions.

 

Key Features

Delivering Performance

  • Supporting small to large system configurations
  • Support for frequency-domain IQ transport
  • Support for various functional split between RU and BBU
  • Supports 10G/25G Ethernet MAC ports
  • Agnostically supports multiple synchronization schemes
  • Wide flexibility for configuring

Easy to use

  • Testbench with typical system configuration and examples
  • Easy integration

Silicon Agnostic

  • Targeting both ASICs and FPGAs
Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual and Release Note.
  • Simulation Environment, including Simple Testbed, Test case, Test Script.
  • Access to support system and direct support from Comcores Engineers.

Block Diagram

eCPRI IP core block diagram

Silicon agnostic and highly scabale implementation of the eCPRI standard.

eCPRI Advantages & Benefits

Test Environment

eCPRI IP is tested against a VIP model in UVM regression for full functional coverage

Silicon Agnostic

Optimized for ASIC but can be synthesized for most FPGAs

 

Interoperability Tested

Used in the field and tested against CPRI references

Radio Expertise

IP with rich feature set designed by pioneers in radio solutions

Active Support

All support is actively provided by engineers directly

Solutions at Work

Packet fronthaul for efficient 5G networks

The eCPRI specification specifies how radio signals are sent across a packet network. The root networks are not stipulated, but may comprise IP/UDP and/or Ethernet.

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5G Radio Solutions

eCPRI is an interface that moves data from RRUs to baseband units, and it is a critical technology in 5G for data encapsulation and decapsulation, control, synchronization, and management of data.

Click to read more 

Why Work with Chip Interfaces

Interoperability Tested

Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.

Faster time to Market

Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.

Quality guaranteed

Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance. 

Reduced Total cost

Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.