Ethernet PCS 100G/200G/400G/800G/1.6T
Silicon agnostic, highly configurable Ethernet PCS IP for Ultra High Speeds
Overview
Chip Interfaces 100G-1.6T Ethernet PCS IP core is a silicon agnostic implementation of the Physical Coding Sublayer (PCS) described in the Ethernet standard IEEE 802.3 and is compliant with Clause 82 of the IEEE 802.3-2022 and Clause 119, Clause 172 and Clause 175 of the IEEE 802.3dj specification. 100G-1.6T Ethernet PCS IP from Chip Interfaces provides an interface between the Media Access Control (MAC) and Physical Medium Attachment (PMA) through a 32 FEC-lane parallel interface to the PMA and offers an n-bit TDM GMII interface or parallel n-bit GMII interface on the other MAC Side.
Chip Interfaces 100G-1.6T Ethernet PCS IP core is verified using advanced methodologies for RTL design, HW verification, and interoperability testing. It has been optimized for size and is a rigorously tested solution to speed up project timelines. The 100G-1.6T Ethernet PCS IP supports multiple links within one IP core with options of 4x100G, 4x200G, 2x400G 1x800G, 1×1.6T bit links.
Key Features
Delivers Performance
- Supports Ethernet speed up to 1.6T bits
- Complete 1.6TBASE-R with RS-FEC solution
- Can be used in common 100G-1.6T Ethernet PHY applications
Highly Configurable
- Configurable for several operating modes and speeds
- Works with multiple PMA designs (Serdes links of 25G 56G 112G 224G etc.)
- Channelized n-bit GMII or Standard n-bit GMII interface to MAC layer
Easy to Use
- BUS2IP is the default Control Interface, with AXI, APB, being optional
- Easy interfacing to standard MACs
- Can be delivered with integrated MAC for plug and play
- Includes test pattern Generator/Checker
Silicon Agnostic
- Designed in SystemVerilog and targeting ASICs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request
Block Diagram
Ethernet PCS 100G - 1.6T Advantages & Benefits
Test Environment
Ethernet PCS 100G-1.6T IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
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