Interlaken Hardware Platform
Hardware platform to demonstrate the Interlaken IP
Overview
Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. The Interlaken HW Platform is a system built on the VCU 118 HW platform consisting of 2 Interlaken IP instances as well as packet generators and checkers connected to the host system console via a JTAG interface.
The platform allows running targeted tests, excercising the Interlaken protocol and its features as well as serving as a demonstration of how an interlaken system is built by demonstrating a physical instantiation with live data running through off PCB loopback. A reference design for implementing Interlaken on Ultrascale VCU 118 is also available, achiving the maximum available Line Rate of the card at 28 Gbps.
Key Features
Delivering Performance
- Up to 28 Gbps line rate on VCU 118
- MAC Layer with fast AMBA CXS interface
- Highly configurable PCS layer with Retransmission and RS-FEC Extension
- 64B 67B encoding/decoding supported
- SystemVerilog random regression tested
- Reference Design Available
Deliverables
The JESD204C Hardware Platform is designed to be easy to use and includes the following:
- Solid documentation including integration guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Easy to use step-by-step instructions.
- No special software is required.
- Strong engineering support for integration and bring-up, directly from Chip Interafces engineers.
Block Diagram
Interlaken Advantages & Benefits
Test Environment
Interlaken IP is tested in a UVM based regression environment for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASIC and FPGA technologies
Interoperability Tested
Interlaken IP is interoperability tested with leading PHY providers and other market available Interlaken solutions
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Solutions at Work
Interlaken unlocking full AI chip potential
The Interlaken IP, a high speed chip-to-chip interface protocol, is vital for AI chip networking.
Interlaken bridging FPGAs and ASICs
The Interlaken IP easily integrates FPGAs and ASICs, allowing for efficient data transport.
Interlaken solving Ethernet Aggregation
The Interlaken IP plays a crucial role in Ethernet aggregation scenarios, particularly in networks that require high-speed data consolidation and delivery.
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
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Interlaken unlocking full AI chip potential
The Interlaken IP, a high speed chip-to-chip interface protocol, is vital for AI chip networking. Interlaken offers seamless connectivity in applications such as data centers, where numerous AI accelerator chips work together to achieve high-performance computation. AI chips use their high bandwidth and low latency capabilities to efficiently exchange huge amounts of data, synchronize operations, and improve overall system throughput. Whether distributing workloads or directing complicated AI workflows, Interlaken IP increases network efficiency and unleashes AI chip potential.
Interlaken bridging FPGAs and ASICs
The Interlaken IP easily integrates FPGAs and ASICs, allowing for efficient data transport. Interlaken enhances communication in instances where an FPGA serves as a flexible accelerator and an ASIC provides optimal performance.
The FPGA offloads computing to the ASIC, increasing overall system efficiency. Interlaken optimizes communication in data centers and networking equipment by combining flexibility and performance via hardware acceleration.
Interlaken solving Ethernet Aggregation
The Interlaken IP plays a crucial role in Ethernet aggregation scenarios, particularly in networks that require high-speed data consolidation and delivery. Consider a telecoms service provider’s network, where multiple Ethernet interfaces from different devices must be integrated to maximize network resources.
The Interlaken IP works easily with Ethernet switches and routers, merging numerous Ethernet streams into a single, high-bandwidth communication link. This consolidation improves network scalability, reduces latency, and optimizes bandwidth utilization.
Interlaken IP meets the demands of modern high-performance networking applications by ensuring optimal data transfer and distribution, whether aggregating Gigabit Ethernet links or merging 10 Gigabit Ethernet connections.