Interlaken
World-class, industry-leading, highly scalable, silicon- and PHY-agnostic IP core with 116 Gbps line rate, interoperability tested with leading Serdes providers
Overview
Interlaken is a scalable chip-to-chip protocol, which ensures the integrity of reliable data transfer and managing data flows to prevent data overload. The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. Our Interlaken controller supports up to 2.6 Tbps high-bandwidth performance and comes with an integrated Media Access layer.
The Interlaken Controller can be widely used in chip-to-chip transfers, it has an extensive feature-set available and allows scalability in number of logic channels (up to 2048), lanes (up to 48) and lane speed (up to 56 Gbps). The IP core is heavily tested in SystemVerilog random regression environment
Key Features
Delivering Performance
- MAC layer with fast AMBA CXS interface
- PCS layer highly configurable with up to 48 lanes
- Multi-lane configurations, up to 48 lanes
- 64B 67B encoding/decoding supported
- Supports up to 2048 logic channels
- Programmable Meta Frame lengths
- Programmable Interlaken Bursts: Short from 32 and Max up to 1024 Bytes
- Flow control support
- Mode of operation: Packet mode and Interleave mode supported
- Re-transmit
- Interlaken Dual Calendar
- Look-Aside
- FEC support
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Programming Register Specification.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and SSynopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request.
Block Diagram
The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. It delivers all features of the standard and includes Retransmission and RS FEC Standard extensions.
The solution consists of combined TX and RX data paths with PCS, MAC and Protocol layers included. In Band Flow control over the data lanes and Out of Band Flow control over a separate interface are available.
Error recovery is made possible via the Retransmit extension. Error correction and PAM 4 encoding with Line rates up to 116Gbps is made possible with the RS FEC extension.
Interlaken Hardware Platform & Reference Design
The Interlaken IP core is a highly optimized silicon and PHY agnostic implementation of the Interlaken Protocol version 1.2 targeting both ASICs and FPGAs. The Interlaken HW Platform is a system built on the VCU 118 HW platform consisting of 2 Interlaken IP instances as well as packet generators and checkers connected to the host system console via a JTAG interface.
Interlaken Advantages & Benefits
Test Environment
Interlaken IP is tested in a UVM based regression environment for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASIC and FPGA technologies
Interoperability Tested
Interlaken IP is interoperability tested with leading PHY providers and other market available Interlaken solutions
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Latest Blogs
UA Link vs Interlaken: What you need to know about the right protocol for AI and HPC interconnect fabrics
AI and high-performance computing (HPC) workloads are growing steadily and the need for establishing high performance and low-latency interconnect links is placing pressure on interconnect technology.
Why Interlaken is a great choice for architecting chip to chip communications in AI chips
Why Interlaken Protocol is a great choice for addressing the architecture and design requirements in chip to chip communications for Artificial Intelligence chips
What is Interlaken protocol for Chip to Chip interface?
Interlaken provides a standardized serial interface that is agnostic of underlying SerDes implementations. It ensures reliable transfer of data over a configurable number of physical connections and can be configured to support multiple lane configurations. The...
Solutions at Work
Interlaken unlocking full AI chip potential
The Interlaken IP, a high speed chip-to-chip interface protocol, is vital for AI chip networking.
Interlaken bridging FPGAs and ASICs
The Interlaken IP easily integrates FPGAs and ASICs, allowing for efficient data transport.
Interlaken solving Ethernet Aggregation
The Interlaken IP plays a crucial role in Ethernet aggregation scenarios, particularly in networks that require high-speed data consolidation and delivery.
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
Interlaken unlocking full AI chip potential
The Interlaken IP, a high speed chip-to-chip interface protocol, is vital for AI chip networking. Interlaken offers seamless connectivity in applications such as data centers, where numerous AI accelerator chips work together to achieve high-performance computation. AI chips use their high bandwidth and low latency capabilities to efficiently exchange huge amounts of data, synchronize operations, and improve overall system throughput. Whether distributing workloads or directing complicated AI workflows, Interlaken IP increases network efficiency and unleashes AI chip potential.
Interlaken bridging FPGAs and ASICs
The Interlaken IP easily integrates FPGAs and ASICs, allowing for efficient data transport. Interlaken enhances communication in instances where an FPGA serves as a flexible accelerator and an ASIC provides optimal performance.
The FPGA offloads computing to the ASIC, increasing overall system efficiency. Interlaken optimizes communication in data centers and networking equipment by combining flexibility and performance via hardware acceleration.
Interlaken solving Ethernet Aggregation
The Interlaken IP plays a crucial role in Ethernet aggregation scenarios, particularly in networks that require high-speed data consolidation and delivery. Consider a telecoms service provider’s network, where multiple Ethernet interfaces from different devices must be integrated to maximize network resources.
The Interlaken IP works easily with Ethernet switches and routers, merging numerous Ethernet streams into a single, high-bandwidth communication link. This consolidation improves network scalability, reduces latency, and optimizes bandwidth utilization.
Interlaken IP meets the demands of modern high-performance networking applications by ensuring optimal data transfer and distribution, whether aggregating Gigabit Ethernet links or merging 10 Gigabit Ethernet connections.