JESD204C Hardware Platform
Hardware platform to demonstrate the JESD204C IP
Overview
The JESD204C Hardware Platform is a system built on the VCU 118 HW platform. It consists of two JESD204C IP instances (Transmitter and Receiver), packet generators, and checkers connected to the host system console via a JTAG interface.
The platform allows running targeted tests, excercising the JESD204C protocol and its features as well as serving as a demonstration of how a JESD204C system is built by demonstrating physical instantiation with live data running through an off-PCB loopback. A reference design for implementing JESD204C on Ultrascale VCU 118 is also available, achiving the maximum available Line Rate of the card at 28 Gbps.
Key Features
Delivering Performance
- Up to 28 Gbps line rate on VCU 118
- Link and Transport Layer
- Supports Subclass 0 and 1
- 64B 66B encoding with CRC3 CRC12 and FC-FEC
- SystemVerilog random regression tested
- Reference Design Available
Deliverables
The JESD204C Hardware Platform is designed to be easy to use and includes the following:
- Solid documentation including integration guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Easy to use step-by-step instructions.
- No special software is required.
- Strong engineering support for integration and bring-up, directly from Chip Interafces engineers.
Block Diagram
JESD204C Advantages & Benefits
Test Environment
JESD204 IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
Interoperability Tested
JESD204 IP is interoperability tested with
- All leading PHY providers
- Key data converter ADC & DAC providers
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Solutions at Work
JESD204 powering AESA Radar
Phased Array Radar (Active Electronically Scanned-Array (AESA)) beamforming is used for improved range, accuracy and capability.
JESD204 for synchronizing multiple ADCs and / or DACs
In 5G wireless radio’s (RRH’s) use of multiple ADCs and / or DACs is faciliated by JESD204.
JESD204 in Quantum Computing
JESD204 protocol with its deterministic latency is an ideal choice for use in quantum computing.
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
JESD204 Powering AESA Radar
Phased Array Radar (Active Electronically Scanned-Array (AESA)) beamforming is used for improved range, better target accuracy and possibility to track multiple targets simultaneously while continuing to search, as the array can be configured to steer multiple beams. Phased-array radars consist of hundreds to tens of thousands of radiating elements, where the phase of each transmitter element can be independently controlled. Each array element also includes a receiver, which collects the energy reflected from the target and is phase locked to the transmitter. JESD204 protocol is the ideal choice for transporting data from the data acquisition system to keep track of timing and phase. Chip Interfaces has delivered JESD204 for multiple AESA chip solutions.
JESD204 for synchronizing multiple ADCs and/or DACs
In 5G wireless radio’s (RRH’s) making use of high speed A/D and D/A converters as well as MIMO RX and TX schemes the ability to synchronize multiple ADCs and/or DACs operating at a high sample rate is essential.
By doing this signal sampling, synthesis, and timing across multiple data converters is maintained to ensure minimum complexity of the interfaces and highest signal quality.
Chip Interfaces has delivered JESD204 for multiple 5G chip solutions.
JESD204 in Quantum Computing
Arbitrary Waveform Generators (AWGs) are key components of the control system in a Quantum Computer. AWGs are essential for manipulating qubits through precise waveform generation, which for further processing needs the usage of ADCs and DACs.
These are used for control and readout of the qubit states. High-speed serial data interfaces towards ADCs and DACs are needed and precise timing information is more relevant than ever. This makes the JESD204 protocol with its deterministic latency an ideal choice for use in quantum computing.
The set-up effort of a quantum computation is great and the field of quantum error correction is well established. It makes sense to protect the computation results of captured q-bit states through the data link with error correction as well.
For Error Correction, the JESD204C IP offers a Fire Code FEC and JESD204D offers a Reed Solomon FEC that can offer the improved link BER. Chip Interfaces has delivered its JESD204 IP for a Quantum Computer project.