JESD204E
Early adopter version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters
Overview
The JESD204E Controller IP from Chip Interfaces is an early adopter’s version of the upcoming revision of the JEDEC standard for Serial Interface for Data Converters. The JESD204-E IP core supports the UCIe Optimized Link Layer, a dedicated mode to run JESD over UCIe Modules with Line rates up the 64Gbps per bump, and a JESD204D backwards compatible mode called the Unified Link Layer with line speeds up to 116Gbps with PAM4 and 58Gbps with NRZ and full FEC support. It can also include full backwards compatibility with 32.5 Gbps JESD204C.1 64b 66b link layer and 16 Gbps JESD204B 8b 10b link layer.
The IP core enables quick and reliable deployment of the transmitter (TX), the receiver (RX) link layer and comes optionally with a tightly integrated transport layer, that can dynamically be configured to handle any Multiple-Converter Device Alignment, Multiple Lanes (MCDA-ML) requirements. The IP comes with the widest parameter set available and has gone through extensive testing in a UVM regression environment.
Key Features
Delivering Performance
UCIe Optimized Link Layer (UOPT) supports UCIe 3.0 Physical Layer with data rates up to 64Gbps for Die-to-Die based chiplet applications
Unified Link Layer for Serdes Line rates up to 116 Gbps, with support for 1-24 lanes and 1-96 converters
Backwards compatible with JESD204D with RS-FEC (544,514), RS-FEC (528,514), RS-FEC (272,258), RS-FEC (144,130) and RS-FEC (136,130)
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request.
Block Diagram
JESD204E from Chip Interfaces is a early adopter solution with integrated transport and link layers, optional backward compatibility with JESD204B/C, and support for flexible multi-lane, multi-converter configurations. It enables high-speed connectivity to UCIe and SerDes interfaces using NRZ and PAM4, while incorporating framing, scrambling, CRC/ECC, synchronization, deskew, and centralized register control to ensure deterministic and reliable data transfer.
JESD204E Advantages & Benefits
Test Environment
JESD204 IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
Interoperability Tested
JESD204 IP is interoperability tested with
- All leading PHY providers
- Key data converter ADC & DAC providers
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Latest Blogs
JESD204 Frame Mapping explained from converter samples to lanes
The JESD204 Transport Layer oversees converter data mapping onto a set of JESD204 Lanes. The nature of these lanes is dependent on the version of the JESD204 standard and a function of the PCS and over the years despite the Serdes technology changing with…
Multiple ways JESD204 performs bitstream alignment
Bitstream alignment is a function of the Receiver (RX), it is the first functional block of the receiver right after the clock domain crossing (CDC) and gear boxing which are quite generic Serdes adaptation layer that can be found in almost every design working with a Serdes
What is JESD204B? Quick summary of the standard
The JESD204B Standard enables the establishment of high-speed serial links between a Controller and ADC and DAC converters with Deterministic Latency. One of the significant changes made in this standard is the increase in specified Line Rates …
How JESD204 Self-Synchronizing Receiver works: An in-depth look
The JESD204 Standard has undergone several iterations since its initial release in April 2006, the Serdes capabilities and required encodings have been improving and adapting along the way. With the release of JESD204C and later JESD204D standards the Transmitter and...
What is JESD204C? A quick glance at the standard
JESD204C standard at a glance The JESD204C standard enables establishing high-speed serial links between a Controller and ADC and DAC converters. JESD204C was first published in December of 2017 as an iteration of the JESD204B Standard published six years prior in...
Bridging Analog and Digital worlds at high speed with the JESD204 serial interface
To meet the increased demand for converter speed and resolution, JEDEC proposed the JESD204 standard describing a new efficient serial interface to handle data converters. In 2006, the JESD204 standard offered support for multiple data converters over a single lane...
Solutions at Work
JESD204 powering AESA Radar
Phased Array Radar (Active Electronically Scanned-Array (AESA)) beamforming is used for improved range, accuracy and capability.
JESD204 for synchronizing multiple ADCs and / or DACs
In 5G wireless radio’s (RRH’s) use of multiple ADCs and / or DACs is faciliated by JESD204.
JESD204 in Quantum Computing
JESD204 protocol with its deterministic latency is an ideal choice for use in quantum computing.
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
JESD204 Powering AESA Radar
Phased Array Radar (Active Electronically Scanned-Array (AESA)) beamforming is used for improved range, better target accuracy and possibility to track multiple targets simultaneously while continuing to search, as the array can be configured to steer multiple beams. Phased-array radars consist of hundreds to tens of thousands of radiating elements, where the phase of each transmitter element can be independently controlled. Each array element also includes a receiver, which collects the energy reflected from the target and is phase locked to the transmitter. JESD204 protocol is the ideal choice for transporting data from the data acquisition system to keep track of timing and phase. Chip Interfaces has delivered JESD204 for multiple AESA chip solutions.
JESD204 for synchronizing multiple ADCs and/or DACs
In 5G wireless radio’s (RRH’s) making use of high speed A/D and D/A converters as well as MIMO RX and TX schemes the ability to synchronize multiple ADCs and/or DACs operating at a high sample rate is essential.
By doing this signal sampling, synthesis, and timing across multiple data converters is maintained to ensure minimum complexity of the interfaces and highest signal quality.
Chip Interfaces has delivered JESD204 for multiple 5G chip solutions.
JESD204 in Quantum Computing
Arbitrary Waveform Generators (AWGs) are key components of the control system in a Quantum Computer. AWGs are essential for manipulating qubits through precise waveform generation, which for further processing needs the usage of ADCs and DACs.
These are used for control and readout of the qubit states. High-speed serial data interfaces towards ADCs and DACs are needed and precise timing information is more relevant than ever. This makes the JESD204 protocol with its deterministic latency an ideal choice for use in quantum computing.
The set-up effort of a quantum computation is great and the field of quantum error correction is well established. It makes sense to protect the computation results of captured q-bit states through the data link with error correction as well.
For Error Correction, the JESD204C IP offers a Fire Code FEC and JESD204D offers a Reed Solomon FEC that can offer the improved link BER. Chip Interfaces has delivered its JESD204 IP for a Quantum Computer project.