MIPI I3C IP solutions
High performance, versatile, highly configurable and MIPI I3C protocol compliant IP solutions
Overview
The MIPI I3C Controller IP is a highly optimized and technology agnostic implementation of the MIPI I3C v.1.1.1 standard targeting both ASIC and FPGA technologies. The Chip Interfaces MIPI I3C IP is used to connect multiple Targets to one or more Controllers with Secondary controllers having the capability to take ownership of the bus. The IP can act as the Bus Controller or Secondary Controller with the inclusion of the Target Engine, it is also possible to set up as a simple Target or Composite Device with multiple Virtual Targets. The MIPI I3C IP from Chip Interfaces supports SDR and HDR transmission modes over a single or multiple lanes allowing it to reach transfer speeds of up to 100 Mbps. The Chip Interfaces MIPI I3C Controller IP is backward compatible with MIPI I3C versions 1.1 and 1.0, as well as with I2C. The Application data interface follows the TCRI v1.0 specification.
The Chip Interfaces MIPI I3C Controller IP core has been heavily tested in System Verilog random regression environment.
Key Features
Delivering Performance
• Fully compliant with MIPI I3C v1.1.1 Specification
• TCRI v1.0 Compliant
• Supports Bus with Multiple Controllers
• Supports Hot Join mechanism
• Supports all I3C CCC common command codes
• Supports SDR, HDR-DDR, HDR-TSP/TSL, HDR-BT
• Supports Multi Lane operation (all formats)
• Supports Async Modes 0-3
• Supports Target Reset
• Supports Device to Device tunneling (D2DT)
• Supports Early Termination
• Supported Roles:
• Controller
• Secondary Controller
• Target
• Composite device with Virtual Targets
Easy to use
- Solid documentation including an integration guide
- Easy to use RTL test environment
- No special software is required
- Strong engineering support for bring-up
Robust
- UVM based Verification
- Lint/CDC checked
Silicon Agnostic
- Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, and Test Script.
- Basic RTL Test Bench
- Synthesis Scripts
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report, Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request.
Controller Role
The MIPI I3C Controller IP core is a highly optimized Silicon Agnostic implementation of the MIPI I3C protocol version 1.1.1 and MIPI TCRI v1.0. It is used to connect I3C and I2C target devices over a shared 2-wire bus, targeting both ASIC and FPGAs. It delivers all features of the standard and allows for the ability to configure included features.
The IP supports Multiple Controllers on the bus with proper Controller handoff procedures to Secondary Controllers as well as I2C and I3C target devices making it possible to build the most complex of systems.
Secondary Controller Role
The MIPI I3C Controller IP core can perform the role of Secondary Controller, combining the functionality of Controller and Target. Initially acting as a target on the bus it can accept Controller role hand-off from the Primary controller assuming it’s new role as the bus controller.
Target Role
The MIPI I3C Target IP core is a highly optimized Silicon Agnostic implementation of the MIPI I3C protocol version 1.1.1. It is used to connect I3C target devices to a Controller over a shared 2 wire bus, targeting both ASIC and FPGA’s. It delivers all features of the standard and allows for great configurability of included features.
Composite Device
The MIPI I3C Design allows for the creation of a composite device, connecting multiple I3C targets over a single physical I3C bus connection. Such an approach reduces the bus capacitance, and other electrical limitations compared to a solution of multiple individual targets connected to the bus.
Even though all targets use the same I3C connection, the host can address and retrieve data from each target independently as needed. This approach saves AISC resources such as area and power consumed.
MIPI I3C Advantages & Benefits
Test Environment
MIPI I3C IP is tested in a UVM based regression environment for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
Active Support
All support is actively provided by engineers directly
Solutions at Work
MIPI I3C an efficient solution for integration of sensors in mobile devices
The Chip Interfaces MIPI I3C IP Core offers a powerful, efficient solution for integrating multiple sensors in mobile devices.
MIPI I3C for Advanced Driver Assistance Systems (ADAS)
The Chip Interfaces MIPI I3C IP Core is engineered to meet the demanding needs of Advanced Driver Assistance Systems (ADAS) and other automotive applications, providing a high-speed, low-latency interface.
MIPI I3C for Industrial Automation
The Chip Interfaces MIPI I3C IP Core offers a cutting-edge solution for Industrial Automation, providing the real-time communication needed for synchronized multi-sensor operations in complex industrial settings.
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
MIPI I3C an efficient solution for integration of sensors in mobile devices
The Chip Interfaces MIPI I3C IP Core offers a powerful, efficient solution for integrating multiple sensors in mobile devices, providing a seamless communication interface between the application processor and various sensors like accelerometers, gyroscopes, and environmental sensors.
By leveraging the advanced features of the I3C protocol, including high-speed data transfer (up to 100 Mbps), in-band interrupts, and dynamic address assignment, Chip Interfaces’ IP core optimizes both performance and power consumption. This enables mobile device manufacturers to design slimmer, more energy-efficient products with enhanced sensor responsiveness, making it ideal for applications such as motion tracking, environmental monitoring, and user interaction in smartphones and tablets. The backward compatibility with I2C further simplifies integration, allowing device makers to easily transition to next generation I3C technology.
MIPI I3C for Advanced Driver Assistance Systems (ADAS)
The Chip Interfaces MIPI I3C IP Core is engineered to meet the demanding needs of Advanced Driver Assistance Systems (ADAS) and other automotive applications, providing a high-speed, low-latency interface for connecting multiple sensors and cameras to the central processing unit.
With its support for data rates up to 100 Mbps and real-time in-band interrupts, the I3C IP core enables seamless communication between critical components such as LiDAR, radar, and cameras, ensuring synchronized, real-time decision-making in safety-critical environments. Its efficient power consumption and reduced pin count simplify sensor network wiring, which is crucial for space-constrained automotive designs.
Additionally, the I3C protocol’s ability to integrate both legacy I2C devices and newer, high-performance sensors allows for flexible and scalable system architectures, making it the ideal solution for the next generation of intelligent, connected vehicles.
MIPI I3C for Industrial Automation
The Chip Interfaces MIPI I3C IP Core offers a cutting-edge solution for Industrial Automation, providing the real-time communication needed for synchronized multi-sensor operations in complex industrial settings.
With data rates up to 100 Mbps and advanced features such as in-band interrupts and dynamic address assignment, the I3C IP core ensures fast, reliable data exchange between various sensors and control systems. The synchronization capability is crucial for applications like robotics, smart manufacturing, and factory automation, where precise and coordinated sensor responses are essential.
The I3C protocol’s efficiency in power usage and reduced wiring simplifies the integration of multiple sensors, while backward compatibility with I2C supports seamless upgrades from legacy systems. By enhancing both performance and scalability, Chip Interfaces’ I3C IP core is a perfect fit for creating intelligent, responsive industrial environments