MIPI RFFE Slave 

Overview

The MIPI RFFE Slave controller IP is a highly optimized and technology and PHY agnostic implementation of the MIPI RFFE v.3.1 standard targeting both ASIC and FPGA technologies. This IP is used to connect a digital RFIC to RF front end components, like Power Amplifiers (PA), Low-Noise Amplifiers (LNA), filters, switches, power management modules, Antenna Turner and Sensors,which are considered RFFE Slaves. This MIPI RFFE Slave IP is backward compatible with MIPI RFFE components version 3.0, 2.1, 2.0 and 1.0.

The IP-core has been rigorously tested in System Verilog random regression environment.

 

Key Features

Delivering Performance

  • Fully compliant with MIPI RFFE v3.1 Specification
  • Supports all RFFE Slave commands
  • Support Standard, Timed and Mappable Triggers
  • Supports all USID Prgramming procedures: 1, 2 and 3
  • Supports wide range of clock frequencies up to maximum 52 MHz
  • Configurable number of type of registers

Easy to use

  • Solid documentation including integration guide
  • Easy to use RTL test environment
  • No special software required
  • Strong engineering support for bring-up

Robust

  • UVM based Verification
  • Lint/CDC checked

Silicon Agnostic

  • Targeting both ASICs and FPGAs
Deliverables

The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:

  • Solid documentation, including User Manual, Release Note and Quick Start Guide.
  • Simulation Environment, including Simple
  • Testbed, Test case, Test Script.
  • Basic RTL Test Bench
  • Synthesis Scripts
  • Synopsys Lint and CDC Waivers
  • Synopsys CDC SGDC Files
  • Synopsys Constraint Files

Block Diagram

MIPI RFFE Slave controller IP block diagram

The MIPI RFFE Slave IP core is a highly optimized Silicon Agnostic implementation of the MIPI RFFE protocol version 3.1, used to connect a digital RFIC to RF Front end components, targeting both ASIC and FPGA’s. It delivers all features of the standard and allows for great configurability of features.

The IP support a configurable amount of slave device registers in 3 separate groups. Making it possible to build the most complex of systems.

Trigger remapping, and timed trigger operation, allow to make efficient use of the slave registers via the shadow register mechanism, coordinating the register value changes to specific points in time.

Trigger remapping, and timed trigger operation, allow to make efficient use of the slave registers via the shadow register mechanism, coordinating the register value changes to specific points in time.

MIPI RFFE Advantages & Benefits

Test Environment

MIPI RFFE IP is tested in a UVM based regression environment for full functional coverage

Silicon Agnostic

Designed in Verilog and targeting both ASICs and FPGAs

 

Active Support

All support is actively provided by engineers directly

Solutions at Work

MIPI RFFE reshaping 5G connectivity

The integration of MIPI RFFE (Radio Frequency Front-End) IP is transforming the future of mobile wireless connection in the constantly evolving environment of 5G systems.

Click to read more 

MIPI RFFE driving Automotive connectivity

Innovation is a hallmark of the automotive industry and MIPI RFFE can play a crucial role in catalysing the innovation trends , enabling enabling seamless connectivity and communication within Connected, Automated, Shared, and Electrified (CASE) vehicles. 

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MIPI RFFE empowering Mobile devices

The Mobile Industry Processor Interface (MIPI) Radio Frequency Front-End (RFFE) is an essential component of mobile devices that enhances wireless communication and battery efficiency. 

Click to read more 

Why Work with Chip Interfaces

Interoperability Tested

Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.

Faster time to Market

Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.

Quality guaranteed

Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance. 

Reduced Total cost

Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.