ORAN
Highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface
Overview
Chip Interfaces ORAN IP core is a highly scalable and silicon agnostic implementation of the interoperable O-RAN WG4 defined 7.2x interface for deployment in O-DU and O-RU products, targeting any ASIC, FPGA or ASSP technologies.
The ORAN over eCPRI implementation builds on long-time experience designing CPRI and Radio-Over-Ethernet solutions for fronthaul and delivers a flexible engine that is prepared for tight integration with software applications.
The IP is designed to meet or exceed the requirements of radio systems, base band systems, fronthaul switches or advanced test systems. The speed optimized core can handle any solutions reaching from the “small footprint” to the most complex applications running 25 Gbps. The IP can dynamically be configured to handle wireless multi-mode radio systems enabling high-performance throughputs required by 4G and 5G wireless solutions.
Key Features
Richly Featured
- Support for frequency-domain IQ transport
- Supports 10G/25G Ethernet MAC ports
- O-RU and O-DU variants available
- Multiple Section Extension Types Supported
- Wide flexibility for configuring
Silicon Agnostic
- Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual and Release Note.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Synopsys Lint and CDC (optional)
Block Diagram
ORAN IF IP Advantages & Benefits
Test Environment
ORAN IF IP is Tested in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting ASICs and FPGAs
System Integration
Integration support with Ethernet components for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
CPRI used in both 4G and 5G radio solutions
For 4G remote radio heads CPRI is an essential component for connectivity to the baseband. The CPRI is providing full synchronization and supports line rates up to 24Gbps. Chip Interfaces has deployed multiple solutions for RRH digital front ends (DFE's) and has a deep understanding of the radio design and the associated standards.
CPRI used in aggregators for mapping and demapping of CPRI legacy connectivity into Ethernet
Advent of 5G coupled with new functional splits between the based and radio, has made the building of a packet based fronthaul system a possibility. This packet based fronthaul system can be achieved either by converting the CPRI streams into eCPRI using baseband processing or mapping of CPRI frames into Ethernet Packets also known as Radio over Ethernet (RoE).
Chip Interfaces have proven solutions available for RoE that can convert CPRI into formats that can be transported on Ethernet and be used to aggregate traffic from different sources like eCPRI and CPRI into the same transport link.