UA Link PCS
Silicon agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification
Overview
The Chip Interfaces UA Link PCS IP Core is a high-performance, silicon-agnostic and fully compliant Physical Coding Sublayer (PCS) implementation of UALink_200 specification. Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.
This IP core bridges the UALink Data Link Layer (DL) to the Physical Medium Attachment (PMA), ensuring optimized flit to codeword mapping, forward error correction (FEC), and alignment marker handling as defined in UALink_200 Standard. It is ideal for systems requiring 200–800 Gbps per Link/Station with industry leading signal integrity and interoperability.
Key Features
Delivering Performance
Supports UALink signaling 100GBASE-KR1/CR1 up to 800GBASE-KR4/CR4
Complete UALink 200 PCS and RS solution compliant with UALink_200 Rev 1.0
Built on IEEE 802.3 foundation: PCS based on Clause 82, 119, and 172 with RS based on Clauses 81, 117, and 170
Native DL Flit-to-RS(544,514) codeword alignment for minimum latency
Deterministic Flit Alignment: 640B DL Flit to 680B codeword mapping
Integrates directly with Chip Interfaces 8:1, 16:2, 32:4, capable PMA layer
Highly Configurable
Supports multiple bifurcation modes: 1×4, 2×2, or 4×1 lane configurations
Selectable FEC interleave modes to trade off latency vs error correction
64B/66B encoded flit interface to the UALink Data Link layer
Easy to Use
BUS2IP is the default Control Interface, with AXI and APB wrappers
Seamless integration with UALink Data Link layer IP
Can be delivered with integrated Chip Interfaces PMA
Silicon Agnostic
Designed in SystemVerilog and targeting ASICs
Verified using advanced methodologies for RTL design, hardware verification
Suitable for UALink accelerator endpoints and high-radix UALink switches
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request.
Block Diagram
UA Link PCS Advantages & Benefits
Test Environment
UA Link PCS IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
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