UA Link DL
Silicon agnostic and fully compliant implementation of UALink_200 specification
Overview
The Chip Interfaces UA Link DL IP Core is a high-performance, silicon-agnostic and fully compliant Data Layer implementation of UALink_200 specifi cation. Designed for seamless integration into accelerator, switch, and SoC designs, it delivers deterministic low-latency, robust error correction, and compatibility with multiple high-speed Ethernet-derived link rates.
This IP core bridges the UALink Transaction Layer (TL) to the UA Link Ethernet Physical Coding Sublayer (PCS), ensuring optimized fl it packing and unpacking, coordinating changes to the link, and providing a UART mechanism for fi rmware-controlled sequence passing as defi ned in UALink_200 Standard. It is ideal for systems requiring 200–800 Gbps per Link/Station with industry leading signal integrity and interoperability.
Key Features
Delivering Performance
- UALink_200 Specifi cation Compliant: Implements DL functions per Rev 1.0
- Multi-Rate Support : 200 GBASE-KR1/CR1, 400 GBASE-KR2/CR2, 800 GBASE-KR4/CR4
- Tx Pacing/Rx rate adaptation
- Provides a Data Link Layer message service between link partners
- Link Level Replay on 640 Byte fl it basis
- 32 bit CRC for error checking
- Targeting both ASICs and FPGAs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request.
Block Diagram
UA Link PCS Advantages & Benefits
Test Environment
UA Link DL IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
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