UCIe D2D Adapter
Industry Leading, Silicon Proven, 32 Gbps per pin, backed by a complete portfolio of verification tools, PHY interoperability and integration.
Overview
The D2D Adapter for UCIe is a scalable adapter layer between one or more protocol components and the UCIe PHY, which ensures efficient data transfer across the UCIe Link by seamlessly coordinating with the Protocol Layer and Physical Layer. By minimizing logic on the main data path, it delivers a low-latency, optimized pathway for protocol Flits. When handling CXL protocol, the D2D Adapter incorporates ARB/MUX functionality to support multiple simultaneous protocols. For scenarios where the Raw BER exceeds 1e-27, it implements the CRC and Retry scheme defined in the UCIe Specification, ensuring reliable data transport for PCIe, CXL, or other protocols including Streaming protocols.
Additionally, the D2D Adapter manages critical functions such as higher-level Link state machine coordination, parameter exchanges with remote Link partners for protocol options, and power management synchronization when supported. The IP Core is silicon and PHY agnostic implementation of UCIe D2D Adapter following the v2.0 standard, targeting ASIC applications. The IP core is thoroughly tested in System Verilog random regression environment.
The IP comes with the widest parameter set available and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested and integrated with a leading UCIe PHY provider.
Key Features
Delivering Performance
- Ultra Low Latency
- CRC and Retry, or Parity Computation
- Multiple Protocols,
- Multiple Stacks
- Protocol/Stack Arbitration and Multiplexing
- Link State Management
- Protocol and Parameter negotiation
- Silicon Agnostic
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request.
Block Diagram
The Die to Die Adapter IP interfaces to the UCIe Serdes with the Raw Die to Die Interface (RDI) and to the Protocol Layer with the Flit-Aware Die to Die Interface (FDI). The IP is highly customizable and contains blocks for CRC / Retry logic as well as Protocol and Stack Multiplexers
Chip Interfaces UCIe D2D Adapter with Extoll UCIe PHY
The D2D Adapter for UCIe combined with the UCIe PHY form a complete UCIe solution ready to support any protocol layer. The offering consists of two IP parts the D2D adapter from Chip Interfaces and the UCIe PHY from Extoll. Chip Interfaces and Extoll collaborate on UCIe technology to create a complete solution for our customers.
UCIe D2D Adapter Advantages & Benefits
Test Environment
UCIe D2D Adapter IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Latest Blogs
UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
When discussing Universal Chiplet Interconnect Express (UCIe) a lot of, well deserved, focus is placed on the UCIe PHY itself with power and throughput performance, and physical aspects like bump pitch and area utilization…
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
JESD204 Powering AESA Radar
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JESD204 for synchronizing multiple ADCs and/or DACs
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By doing this signal sampling, synthesis, and timing across multiple data converters is maintained to ensure minimum complexity of the interfaces and highest signal quality.
Chip Interfaces has delivered JESD204 for multiple 5G chip solutions.
JESD204 in Quantum Computing
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These are used for control and readout of the qubit states. High-speed serial data interfaces towards ADCs and DACs are needed and precise timing information is more relevant than ever. This makes the JESD204 protocol with its deterministic latency an ideal choice for use in quantum computing.
The set-up effort of a quantum computation is great and the field of quantum error correction is well established. It makes sense to protect the computation results of captured q-bit states through the data link with error correction as well.
For Error Correction, the JESD204C IP offers a Fire Code FEC and JESD204D offers a Reed Solomon FEC that can offer the improved link BER. Chip Interfaces has delivered its JESD204 IP for a Quantum Computer project.