UCIe Protocol Layer: AXI-S
Industry Leading, AXI5-Stream Solution for UCIe D2D Stacks
Overview
The AXI-S Protocol Layer for UCIe is a protocol adapter layer between a Streaming AXI Bus and the FDI interface of the UCIe D2D Adapter. It allows for efficient communication across chiplets using the light weight AXI Streaming Protocol. The IP includes both the TX and RX direction with configurable data bus width and the expected ready valid handshaking with wakeup capability, strb, keep, last indications for data flagging, id, dest for steam identification and routing and the user sideband information.
The IP Core is silicon and PHY agnostic implementation of AXI5 Stream Protocol Layer for UCIe following the v2.0 standard, targeting ASIC applications. The IP core is thoroughly tested in System Verilog random regression environment. The IP comes with a parameter based flexible data bus width and has gone through extensive testing. The IP core is silicon proven, heavily tested in UVM regression environment and has been interoperability tested and integrated with a leading UCIe PHY provider.
Key Features
Delivering Performance
- Configurable Data width
- AXI4 Stream and AXI5 Stream Compliant
- All handshaking features including wakeup
- strb and keep for data flagging
- id and destination for stream identification and routing
- User sideband information supported
- Silicon Agnostic
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request
Block Diagram
The AXI-S Protocol Layer interfaces to the UCIe Die to Die Adapter IP with the Flit-Aware Die to Die Interface (FDI). The IP is customizable in its data width and contains all the necessary features for compliant AXI-S transfers across UCIe.
UCIe Protocol Layer: AXI-S Advantages & Benefits
Test Environment
UCIe AXI-S Protocol Layer is Tested in a UVM regression environment for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
UCIe PHY Integration
PHY Integration support with additional hours or off the shelf UCIe D2D Adapter and UCIe PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Latest Blogs
UCIe D2D Adapter Explained: Architecture, Flit Mapping, Reliability, and Protocol Multiplexing
When discussing Universal Chiplet Interconnect Express (UCIe) a lot of, well deserved, focus is placed on the UCIe PHY itself with power and throughput performance, and physical aspects like bump pitch and area utilization…
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
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