Ultra Ethernet MAC & PCS 100G/200G/400G/800G
Complete, silicon-agnostic implementation of the Ultra Ethernet Transport link layer
Overview
The Chip Interfaces Ultra Ethernet MAC & PCS IP core delivers a complete, silicon-agnostic implementation of the Ultra Ethernet Transport link layer, purpose built for the demanding bandwidth and latency requirements of AI training clusters, high-performance computing (HPC), and hyperscale data center fabrics. Compliant with the Ultra Ethernet Consortium (UEC) Specification v1.0 and the 25/50 Gigabit Ethernet Consortium Low Latency Reed-Solomon Forward Error Correction (LL-RS-FEC) specification v1.0, the core supports port configurations of 1-4x100G, 1-4x200G, 1-2x400G, and 1x800G , providing the flexibility to address the full range of backend scale-out network deployments.
Combining an integrated (MAC), Physical Coding Sublayer (PCS), Link Layer Retry (LLR), and Credit-Based Flow Control (CBFC) into a single cohesive solution, the core provides a robust foundation for lossless, low-latency fabric operation. The LLR sublayer delivers single-link-RTT loss recovery, while CBFC provides lossless delivery across up to 32 virtual channels. Together, LLR and CBFC provide a robust foundation for the lossless, low-latency fabric operation that large scale collective communication workloads demand.
Designed in System Verilog for ASIC targets, the core is delivered with comprehensive documentation, a simulation environment, programming register specifications, SDC timing constraints, and dedicated engineering support enabling confident, accelerated tape-out.
Key Features
Delivers Performance
- Supports Ultra Ethernet speeds from 100G to 800G (4x100G, 4x200G, 2x400G, 1x800G)
- Run-time configurable link topology via software
- Complete integrated MAC + PCS + LLR + CBFC solution in a single IP
- Compliant with Ultra Ethernet Consortium Specification v1.0
Highly Configurable
- RS(544,514) Regular FEC and RS(272,258) Low Latency FEC (Ethernet Technology Consortium LL-RS-FEC)
- Cut-through and Store-and-Forward operation modes
- Up to 32 Virtual Channels, with per-VC CBFC and VC credit pooling
Feature Rich
- UE Link Layer Retry (LLR) for single-link-RTT loss recovery
- UE Credit-Based Flow Control (CBFC) as an alternative to PFC
- UE Control Ordered Sets (CtlOS) natively integrated for LLR and CBFC signaling
- Priority-Based Flow Control (PFC) per IEEE 802.1Q-2022 Clause 36
- UE FEC Statistics for link quality monitoring and MTBPE estimation
- RMON Statistics, Jumbo Frame support, programmable MTU, FCS Check / Insertion
Easy to Use
- APB/AXI-4 Lite or BUS2IP control interface
- TDM channelized AXI Stream interface on client-side
- Easy interfacing to standard SerDes/PMA with lane reorder support
Silicon Agnostic
- Designed in SystemVerilog and targeting ASICs
Deliverables
The IP Core can be delivered in Source code or Encrypted format. The following deliverables will be provided with the IP Core license:
- Solid documentation, including User Manual, Release Note and Quick Start Guide.
- Simulation Environment, including Simple Testbed, Test case, Test Script.
- Timing Constraints in Synopsys SDC format.
- Access to support system and direct support from Chip Interfaces Engineers.
- Test Report , Synopsys SGDC Files and Synopsys Spyglass/Siemens Questa/Verilater Lint, CDC and Waivers available on request
Block Diagram
Ultra Ethernet MAC & PCS 100G - 800G Advantages & Benefits
Test Environment
Ultra Ethernet MAC & PCS 100G – 800G IP is Tested against a VIP model in UVM regression for full functional coverage
Silicon Agnostic
Designed in Verilog and targeting both ASICs and FPGAs
PHY Integration
PHY Integration support with additional hours or off the shelf PHY integration package for quick and efficient deployment
Active Support
All support is actively provided by engineers directly
Why Work with Chip Interfaces
Interoperability Tested
Chip Interfaces Digital IPs, seamlessly interoperable with all leading PHY providers, saves you time and resources. No more compatibility concerns.
Faster time to Market
Chip Interfaces IP cores seamlessly integrate into your projects, saving you time and resources. Full feature testing across multiple tape-outs guarantees rock-solid reliability and peace of mind.
Quality guaranteed
Chip Interfaces IP cores undergo rigorous UVM regression testing for comprehensive functional coverage, lint and CDC checks for rock-solid design, and exhaustive HW tests to guarantee flawless performance.
Reduced Total cost
Chip Interfaces IP cores are proven & pre-tested, slashing integration time and thereby lowering total project costs.
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